1. Field of the Invention
The present invention relates to the field of computer system architecture and in particular, to data transactions using multiple operations which may be interrupted in such architecture.
2. Description Information
With recent emerging technologies, such as the Internet, digital telecommunications, speech processing, sound processing, electronic facsimile and image processing, high performance computer systems and printers are required to process such voluminous data in order to produce adequate results within reasonable response time. Even though faster semiconductors, such as faster CPUs and memory chips, may solve part of the performance problem, compatibility of system architectures between existing systems and a new system is another important consideration because users are reluctant to purchase new software every time they purchase new hardware or vice versa. Thus, increasing system's performance by optimizing an existing architecture often produces more desirable results.
A computer system generally includes a processing unit, memory, I/O interface, and busing arrangements. Each component connects to a system bus or several buses to transfer data between the components. Since a bus can typically only transfer one source data at any given time, bus contention between the components often becomes a major factor of how fast a system can run. Consequently, a more sophisticated busing arrangement for arbitrating the use of buses is quite necessary to have a high performance computer system.
Busing arrangements include some means of bus arbitration that facilitates the sequence of data to be transferred. Such means for arbitrating is usually performed by a bus arbitrator. For example, when a processing unit desires to write data to some other destination component, it signals to the bus arbitrator, which is typically a separate component from the processing unit, that the data is ready and provides an address to which the data is to be written. If multiple system components want to be master of a bus for transferring data, the bus arbitrator prioritizes the data to be transferred and decides which component gets the bus first. Data transfer between system components is normally accomplished by read and write transactions.
FIG. 1 illustrates typical read requests issued by a processing unit on a system address and data ("SysAD") bus 106. In one particular example, a SysAD bus is a bus architecture which interfaces a MIPs R4000 or R5000 series compatible microprocessor from MIPs of Mountain view, Calif., with memory and other components. The processing unit initially samples a read ready signal ("RdRdy") 102 to determine whether an external agent is ready to accept a read request. When the RdRdy 102 is asserted, it indicates that the external agent is ready to accept a read request. In cycle 3, the processing unit issues a first read request, read0 124, on a system command ("SysCmd") bus 108 and addr0 126 on SysAD bus 106. During cycle 3, the processing unit also asserts data valid out ("ValidOut") 109 indicating the data on the buses are valid. The processing unit during cycle 3 also releases mastership of SysAD bus 106 by asserting a release signal ("Release") 104. In a typical SysAD bus architecture, a Release 104 is automatically asserted by the processor during a read request which is accepted. Thus, a read response will follow the read request. The processing unit waits for read response 134 in cycle 4 and receives data0, which is the response of read0, in cycle 5. During cycle 5, the external agent also asserts a valid data in signal ("ValidIn") 107 indicating that the data from the external agent on the SysAD 106 is valid. The external agent further deasserts the RdRdy 102 during cycle (indicating it is not ready to accept a read request) and then in cycle 6 the external agent asserts RdRdy 102 to indicate that it is ready to accept another read request. Two cycles after the assertion of RdRdy, a next read request, read1 136, is issued. As can be seen, there are at least four cycles between the first and second read requests. It will be appreciated that in a typical embodiment, many of the actions which occur in a clock cycle occur at a clock edge, such as a rising edge.
FIG. 2 illustrates a typical busing arrangement for a write request. The processor unit initially samples a write ready signal ("WrRdy") 202 from an external agent to determine whether the external agent is ready to accept a write request. After WrRdy 202 is asserted for two cycles 222, the processor unit in cycle 3 acknowledges that the external agent is ready to accept a write request. In cycle 3, the processing unit issues a first write request, write0 224, on SysCmd bus 108 and addr0 226 on SysAD bus 106. Also, ValidOut 109 is asserted to indicate that the valid data is on the buses. The busing protocol requires at least two unused cycles 232 after a write address and data pair in order to resample WrRdy 202. Moreover, in a possible write mode, an external agent suspends subsequent writes for four system cycles after WrRdy 202 is deactivated. As can be seen, the number of cycles between first and second issuances of write requests can be four system cycles 230, but it may easily take six or more system cycles 240. In a variation of the write request protocols, it has been possible to perform pipelined write requests, such as multiple consecutive write requests, and to reissue a write request which is aborted. However, these protocols do not support multiple consecutive read requests without release of bus mastership between the read requests.
A busing arrangement having an address and data pair every four system cycles is not sufficiently high performance for modern computer systems. It is desirable to have a busing arrangement that can arbitrate buses more efficiently. As will be seen, one embodiment of the present invention provides protocol options that allow an address and data pair at a rate of every two cycles.